“Your first projects aren’t the greatest things in the world, and they may have no money value, they may go nowhere, but that is how you learn – you put so much effort into making something right if it is for yourself.”
Project Name: Yocto Core’s Github!
Dev Board: Nexys A7: 100T
Post Date Date:…… 12/28/2020
Post Updated On:.. 01/07/2021
YoctoC Start Date:. 01/08/2021
YoctoC Deadline:…. 02/01/2021
How do you design a RISC-V Processor? Where do you start?
The entirety of the Yocto-Core Project, including the learning process will be documented. Which makes learning about RISC-V design a more streamlined and concise. I assume the reader has a basic understanding of FPGAs, computer architecture & design, and HDLs. If not, feel free to review the links below.
RISC-V is open source; the future of efficient processing. And what is open source should be open to the public to easily learn. So tag along and join my on this RISC journey!
*I will use this post to horde and document links.
Goals & Features:
Instruction sets “G + A + C” (General Compute, Atomic, Compress)
Simple in design and modularity
Finish project 31 days from start date. (Jan/01/2021)
High performance and efficiency including per clock cycle metrics
Design >> Verification >> Code/Testbench >> HW Verification & Benchmarks
The RISC-V Instruction Specs
RISC-V Main Github Page
RISC-V Reference Card (Instruction set cheat sheet)
Wiki: RISC Extension Naming Scheme
Paper: Optimized RISC-V Five-Sage Pipelining
YouTube Playlist: LMARV-1 Hardware RISC-V! (contains bugs, but is fixed)
YouTube Playlist: LMARV-1: reboot/redesign
PDF: RISC-V CPU Control, Pipelining Single-Cycle RV32-I
YouTube Playlist: Ben Eater’s 8-Bit Breadboard CPU!
YouTube Playlist: MIPS Single-Cycle Architecture
YouTube Playlist: CSCE 611 Fall 2020 Seems to be a good playlist, RISC @ Lecture 9
Digital Design and Computer Architecture (Good intro, but uses MIPS for CPU portion)
Great Book on SystemVerilog: Simulation & Synthesis
Computer Architecture: A Quantitative Approach – 6th Edition